RISC-V三级流水内核RAC101

 Core: RISC-V RV32IM instruction supported, 3 stage pipeline (200MHZ Max), 2 DMA and MPU (Memory Protection Unit)

 Operation conditions: Vcc 2.5V to 3.3V, Vdd 1.0V to 1.2V

 Memories： - 24KB instruction SRAM，separate into 3 banks. - 16 to 32KB data SRAM - Dual 8KB Memio SRAM can be used as data SRAM

 Debug mode: JTAG Interfaces

 IO: - Up to 80 reconfigurable GPIOs - IO remap based on group; each group has 8 pins. - GPA is used for configure, GPG is used for download program

 Communication Interfaces: - 2 QSPI/SPI - 2 Uarts - 2 IICs - 20 PWMS

 Dual 8 channel DMA controller

 Timers： - Four 16-bit timers - One 32-bit timer